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NB3N5573 3.3V, Crystal - To- HCSL Clock Generator
Description
The NB3N5573 is a high precision, low phase noise clock generator that supports PCI Express and Ethernet requirements. The device takes a 25 MHz fundamental mode parallel resonant crystal and generates differential HCSL output at 25 MHz, 100 MHz, 125 MHz or 200 MHz clock frequencies. This device is housed in 5.0 mm x 4.4 mm narrow body TSSOP 16 pin package.
Features
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MARKING DIAGRAM
16 1 TSSOP-16 DT SUFFIX CASE 948F A L Y W G 16 NB3N 5573 ALYWG G
* * * *
* * * *
Uses 25 MHz Fundamental Mode Parallel Resonant Crystal External Loop Filter is Not Required HCSL Differential Output Phase Noise: Offset Noise Power 100 Hz -103 dBc/Hz 1 kHz -118 dBc/Hz 10 kHz -122 dBc/Hz 100 kHz -130 dBc/Hz 1 MHz -132 dBc/Hz 10 MHz -149 dBc/Hz Typical Period Jitter RMS of 1.5 ps Operating Range 3.3 V 10% Industrial Temperature Range -40C to +85C These are Pb-Free Devices
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= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.
VDD X1/CLK 25 MHz Clock or Crystal Clock Buffer Crystal Oscillator X2 BN Phase Detector Charge Pump VCO HSCL Output HSCL Output CLK0 CLK0 CLK1 CLK1 GND S0 S1 OE IREF
Figure 1. NB3N5573 Simplified Logic Diagram
(c) Semiconductor Components Industries, LLC, 2008
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April, 2008 - Rev. 2
Publication Order Number: NB3N5573/D
NB3N5573
S0 S1 NC X1/CLK X2 OE GND NC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD CLK0 CLK0 GND VDD CLK1 CLK1 IREF
Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTION
Pin 1 2 12, 16 4 5 6 7, 13 9 11 10 15 14 3, 8 Symbol S0 S1 VDD X1/CLK X2 OE GND IREF CLK1 CLK1 CLK0 CLK0 NC I/O Input Input Power Supply Input Input Input Power Supply Output HCSL Output HCSL Output HCSL Output HCSL Output Description LVTTL/LVCMOS frequency select input 0. Internal pullup resistor to VDD. See output select table 2 for details. LVTTL/LVCMOS frequency select input 1. Internal pullup resistor to VDD. See output select Table 2 for details. Positive supply voltage pins are connected to +3.3 V supply voltage. Crystal or Clock input. Connect to 25 MHz crystal source or single-ended clock. Crystal input. Connect to a 25 MHz crystal or leave unconnected for clock input. Output enable tri-states output when connected to GND. Internal pullup resistor to VDD. Ground 0 V. These pins provide GND return path for the devices. Output current reference pin. Precision resistor (typ. 475 W) is connected to set the out put current. Noninverted clock output. Inverted clock output. Noninverted clock output. Inverted clock output. Do not connect
Table 2. OUTPUT FREQUENCY SELECT TABLE
S1 L L H H S0 L H L H fCLKout (MHz) 25 100 125 200
Recommended Crystal Parameters
Crystal Frequency Load Capacitance Shunt Capacitance, C0 Equivalent Series Resistance Initial Accuracy at 25 C Temperature Stability Aging C0/C1 Ration
Fundamental AT-Cut 25 MHz 16-20 pF 7 pF Max 35 W Max 20 ppm 30 ppm 20 ppm 250 Max
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NB3N5573
Table 3. ATTRIBUTES
Characteristic ESD Protection Human Body Model Value > 2 kV Level 1 UL 94 V-0 @ 0.125 in 7623
Moisture Sensitivity, Indefinite Time Out of Dray Pack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34
Table 4. MAXIMUM RATINGS (Note 2)
Symbol VDD VI TA Tstg qJA qJC Tsol Parameter Positive Power Supply Input Voltage (VIN) Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder 0 lfpm 500 lfpm (Note 3) TSSOP-16 TSSOP-16 TSSOP-16 Condition 1 GND = 0 V GND = 0 V GND v VI v VDD Condition 2 Rating 4.6 -0.5 V to VDD+0.5 V -40 to +85 -65 to +150 138 108 33 to 36 265 Units V V C C C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. 3. JEDEC standard multilayer board - 2S2P (2 signal, 2 power).
Table 5. DC CHARACTERISTICS (VDD = 3.3 V 10%, GND = 0 V, TA = -40C to +85C, Note 4)
Symbol VDD IDD IDDOE VIH VIL VOH VOL Vcross DVcross Power Supply Voltage Power Supply Current Power Supply Current when OE is Set Low Input HIGH Voltage (X/CLK, S0, S1, and OE) Input LOW Voltage (X/CLK, S0, S1, and OE) Output HIGH Voltage for HCSL Output (See Figure 5) Output LOW Voltage for HCSL Output (See Figure 5) Crossing Voltage Magnitude (Absolute) for HCSL Output Change in Magnitude of Vcross for HCSL Output 2000 GND - 300 660 -150 250 700 0 Characteristic Min 2.97 Typ 3.3 120 Max 3.63 135 65 VDD + 300 800 850 150 550 150 Unit V mA mA mV mV mV mV mV mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Measurement taken with outputs terminated with RS = 33.2 W, RL = 49.9 W, with test load capacitance of 2 pF and current biasing resistor set at 475 W. See Figure 3.
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NB3N5573
Table 6. AC CHARACTERISTICS (VDD = 3.3 V 10%, GND = 0 V, TA = -40C to +85C; Note 5)
Symbol fCLKIN fCLKOUT WNOISE Characteristic Clock/Crystal Input Frequency Output Clock Frequency Phase-Noise Performance fCLKout = 200 MHz @ 100 Hz offset from carrier @ 1 kHz offset from carrier @ 10 kHz offset from carrier @ 100 kHz offset from carrier @ 1 MHz offset from carrier @ 10 MHz offset from carrier Tjitter Period Jitter Peak-to-Peak (Note 6) Period Jitter RMS (Note 6) Cycle-Cycle RMS Jitter (Note 7) Cycle-to-Cycle Peak to Peak Jitter (Note 7) OE tDUTY_CYCLE tR tF DtR DtF Stabilization Time Output Enable/Disable Time Output Clock Duty Cycle (Measured at cross point) Output Risetime (Measured from 175 mV to 525 mV, Figure 5) Output Falltime (Measured from 525 mV to 175 mV, Figure 5) Output Risetime Variation (Single-Ended) Output Falltime Variation (Single-Ended) Stabilization Time From Powerup VDD = 3.3 V 3.0 45 175 175 fCLKout = 200 MHz fCLKout = 200 MHz fCLKout = 200 MHz fCLKout = 200 MHz -103 -118 -122 -130 -132 -149 10 1.5 2 20 10 50 340 340 55 700 700 125 125 20 3 5 35 ps ms % ps ps ps ps ms ps 25 Min Typ 25 200 Max Unit MHz MHz dBc/Hz
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Measurement taken from differential output on single-ended channel terminated with RS = 33.2 W, RL = 49.9 W, with test load capacitance of 2 pF and current biasing resistor set at 475 W. See Figure 3. 6. Sampled with 10000 cycles. 7. Sampled with 1000 cycles.
HCSL INTERFACE
CLK0 RL = 33.2 W RL = 33.2 W CLK0 Zo = 50 W RL = 49.9 W HCSL Driver CLK1 RL = 33.2 W RL = 33.2 W CLK2 Zo = 50 W RL = 49.9 W RL = 49.9 W Zo = 50 W RL = 49.9 W Receiver Zo = 50 W
Figure 3. Typical Termination for Output Driver and Device Evaluation
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NB3N5573
LVDS COMPATIBLE INTERFACE
CLK0 Zo = 50 W 100 W CLK0 Zo = 50 W RL = 150 W NB3N5573 RL = 150 W Receiver 100 W
CLK1
Zo = 50 W 100 W 100 W Zo = 50 W RL = 150 W RL = 150 W LVDS Device Load
CLK2
Figure 4. Typical Termination for LVDS Device Load
700 mV 525 mV 525 mV
175 mV 0 mV
175 mV
tR
340 ps
340 ps
tF
Figure 5. HCSL Output Parameter Characteristics
ORDERING INFORMATION
Device NB3N5573DTG NB3N5573DTR2G Package TSSOP-16 (Pb-Free) TSSOP-16 (Pb-Free) Shipping 96 Units / Rail 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NB3N5573
PACKAGE DIMENSIONS
TSSOP-16 CASE 948F-01 ISSUE B
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
2X
L/2
16
9
J1 B -U-
SECTION N-N J N
L
PIN 1 IDENT. 1 8
0.25 (0.010) M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.15 (0.006) T U
S
A -V-
N F DETAIL E -W-
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
SOLDERING FOOTPRINT*
7.06 1
16X
0.36
16X
1.26
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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EEE CCC EEE CCC
0.65 PITCH
DIMENSIONS: MILLIMETERS
NB3N5573
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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NB3N5573/D

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